The Next Computing Revolution: Bringing Processing Inside Memory
computer.org·18h·
Discuss: Hacker News
Hardware Transactional Memory
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
arxiv.org·1d
🔧Hardware Verification
The Chip That Spoke Lisp
jxself.org·3h
🤖Lisp Machines
Beating the L1 cache with value speculation (2021)
mazzo.li·23h·
CPU Microarchitecture
Hardware Stockholm Syndrome
programmingsimplicity.substack.com·14h·
Discuss: Substack
🔩Systems Programming
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·1d·
Discuss: r/programming
Cache Coherence
The Role of AI in Next-Gen Chip Design
dev.to·1d·
Discuss: DEV
🔧Hardware Verification
Show HN: Blueprintor for Hardware Engineering
zima.run·1h·
Discuss: Hacker News
Homebrew CPUs
LLM Optimization Notes: Memory, Compute and Inference Techniques
gaurigupta19.github.io·23h·
Discuss: Hacker News
💻Local LLMs
CPU Cache-Friendly Data Structures in Go: 10x Speed with Same Algorithm
skoredin.pro·1d·
Discuss: Hacker News
💨Cache Optimization
Qualcomm acquires Arduino, introduces Arduino UNO Q “dual-brain” SBC
cnx-software.com·59m
🦾ARM Cortex-M
We built a CUDA emulator that profiles GPU code with zero hardware
rightnowai.co·15h·
Discuss: Hacker News
🎯Emulator Accuracy
Walrus, A 1M ops/sec, 1 GB/s Write Ahead Log in Rust
nubskr.com·15m·
Discuss: Hacker News
💿ZFS Internals
🔥 How to Make the Best IoT Project using PIC16F877A
hackster.io·3h
🔌Single Board PC
M900 - 10FLS00P00 - Not utilising Cores, seems throttled.
reddit.com·10h·
Discuss: r/homelab
🔌Operating system internals
Why We Need SIMD
parallelprogrammer.substack.com·1d·
Discuss: Substack
📊RISC-V Vectors
State-Compute Replication: Parallelizing High-Speed Stateful Packet Processing
danglingpointers.substack.com·38m·
Discuss: Substack
📡Network Stack
Static Bundle Object: Modernizing Static Linking
medium.com·30m·
Discuss: Hacker News
🔗Static Linking
Why We Created Turso, a Rust-Based Rewrite of SQLite
thenewstack.io·1d
💾SQLite